1. Field of the Invention
The present invention relates to a semiconductor device having a smaller electrostatic capacitance electrode and, more particularly, to an improvement of the structure of an electrode. The present invention also relates to a method for manufacturing such a semiconductor device.
2. Description of the Related Art
There is known a package structure in which an external electrode is directly formed on the surface of a semiconductor chip. Patent Publications JP-2004-79579A and JP-2004-327910A describe such a package structure. With reference to FIG. 4, the outline of the conventional package structure will be described. An array of pad electrodes 33 are formed on the surface of a silicon substrate 31 with an intervention of an insulating film 32, the pad electrodes 33 being connected to the internal electrodes of the internal circuit covered by the insulating film 32. An array of solder balls 34 are mounted on the respective pad electrodes 33, to form external electrodes for connecting to an external circuit such as a printed circuit board. This package structure 30 is known as a so-called wafer-level chip-size package.
To obtain the structure shown in FIG. 4, a semiconductor wafer manufactured by a typical semiconductor fabrication process is used. After the internal circuit, i.e., semiconductor circuit has been formed on the silicon substrate 31, the entire main surface of the semiconductor wafer is covered by the insulating film 32. Then, aluminum pads (not shown) to be connected to the external circuit are exposed by etching the insulating film 32 to form openings therethrough, followed by formation of interconnections 35 using Ti and Cu films in the openings and on the insulating film 32. Subsequently, the pad electrodes 33 and solder balls 34 are consecutively formed on the surface of the Ti/Cu interconnections 35, and thereafter the wafer is divided in to a plurality of chip-size packages. In such chip-size packages, i.e, wafer-level chip-side packages, formation of a plurality of packages can be achieved in block during the wafer stage of the packages. The wafer stage processing simplifies the structure of the packages and the fabrication process thereof, contributing to a reduction in both the package size and fabrication cost.
As described above, in the wafer-level chip-size semiconductor package having the conventional structure, the pad electrodes are formed on the silicon substrate with an intervention of an insulating film, and solder balls are mounted on the pad electrodes, to thereby establish the connection between the pad electrodes and board electrodes formed on a printed circuit board made of, for example, organic resin.
It is known that when such a connection structure is adopted, a stress occurs in the solder balls used for connection to the external circuit, due to a temperature change and a difference in the thermal expansion coefficient between the package, which is made of silicon, and the printed circuit board, which is made of organic resin. Occurrence of an excessive stress, if any, may lead to a disconnection in some cases between the pad electrodes and the external circuit.
As a countermeasure for the above-described problem, there may be considered to increase the diameter of the solder balls to thereby enhance the mechanical strength of the solder balls and the vicinity thereof. However, the use of solder balls having a larger diameter incurs another problem in that a larger electrostatic capacitance is associated between the silicon substrate and the pad electrodes. The larger electrostatic capacitance involves the disadvantage that the propagation delay of the signal increases.
Here, the electrostatic capacitance of the pad electrodes is exemplarily calculated. For the semiconductor package structure having the above configuration, the electrostatic capacitance of the pad electrodes, i.e., the capacitance between the pad electrodes and the silicon substrate is calculated for the case of a variety of the thicknesses of the insulating film.
It is assumed here that the diameter of the pad electrodes is 350 μm; and the dielectric constant ε of the insulating film is 3.5×8.85×10−12 F/m. The results of calculation are shown in Table 1.
TABLE 1Thickness (μm)5.010.020.030.0Capacitance (pF)0.5960.2980.1490.099
The time length (td) required to charge a capacitor having a electrostatic capacitance of Cp=0.1 pF up to a terminal voltage of V=1 volt for the capacitor by using a charge current I of 1=1 mA is calculated herein, by using the following equation:td=Cp×R=Cp×V/I. The time length td thus obtained may be considered to represent the propagation delay of the signal incurred by the electrostatic capacitance. The time length td calculated by the above equation is 0.1 ns, which corresponds to an operating frequency of about 10 GHz for the semiconductor device.
In other words, in order to transmit a high-speed signal having a frequency of 10 GHz or above and a signal current of 1 mA, the electrostatic capacitance of the pad electrodes should preferably be reduced down to 0.1 pF or less. As will be understood from the results shown in Table 1, the preferable thickness of the insulating film is about 30 μm or more in order to reduce the electrostatic capacitance of the pad electrodes down to 0.1 pF or less.
However, the thickness of the silicon substrate used in these days is reduced more and more in order to reduce the thickness of the entire package. For this purpose, the silicon wafer is typically polished after fabrication of the semiconductor circuit therein. If the thickness of the insulating film on the silicon wafer is relatively large, however, a smaller thickness of the polished silicon wafer may sometimes incur a warp of the silicon wafer due to the stress caused by the thick insulating film, making it difficult to perform subsequent processings for the semiconductor wafer.
Curvature radius “r” of a warp of the wafer can be represented by the following equation:r=2Eb/6(1−ν)σd  (1),where E, b, ν, d, σ are the Young's modulus of the substrate, thickness of the substrate, Poisson's Ratio of the substrate, thickness of the insulating film, and stress of the insulating film, respectively. Assuming that the wafer diameter is w, the warped amount “t” of the silicon wafer can be represented by the following equation:t=r{1−sin(cos−1(w/2r))}  (2)If the film stress σ is 100 mega-Pascal (MPa), Young's modulus E of the substrate is 190 giga-Pascal (GPa), and Poisson's Ratio ν of the substrate is 0.07, the warped amount “t” of the wafer can be obtained for a variety of the thickness d of the insulating film, as shown in Table 2.
TABLE 2FilmSubstrateCurvatureWaferWarpedThickness:Thickness:Radius:Diameter:Amount:d μmb μmr mmw mmt mm50.6245162000.2100.6122582000.4200.661292000.8300.640862001.250.16812007.4100.134120015.0200.117020032.5300.111420059.8
As understood from Table 2, for the case where the wafer diameter w is 200 mm and substrate thickness b is 0.6 mm, the warped amount t is as small as 1.2 mm even if the thickness d of the insulating film is 30 μm, which incurs substantially no problem. On the other hand, if the substrate thickness b, which is the wafer thickness, is reduced down to 0.1 mm, the warped amount t is as large as about 60 mm and, therefore, a problem occurs in the transportation of the wafer or an exposure step in a photolithographic process, for example.